The present invention relates to an excess electric current detection and control circuit for electric power source system for supplying an electric power to a semiconductor device to be tested, and in particular, to an excess electric current detection and control circuit for a plurality of power sources working in parallel for supplying a variable electric power to a semiconductor device to be tested by a semiconductor test system.
In testing a semiconductor device by a semiconductor test system, the semiconductor test system has to provide a variable electric power source to the semiconductor device under test to determine whether the device works correctly under the predetermined power level. Thus, the semiconductor test system includes a device power source (DPS) to achieve an electric current setting function to freely provide different levels of electric power to the device under test. If, for example, the device under test drains an electric current which is deemed to be excessive, the device may be determined to be defective.
When an electric current which is excessive to the device under test flows, because for example, the device under: test is defective, an excess electric current detect signal is generated and a predetermined electric current (maximum current level) is maintained to be provided to the device until the test system determines that the device under test has failed in the test. Therefore, in case that one electric power source for a device under test 10 which drains a more source current than specified, the electric power source generates an excess electric current detection signal. The detection signal is proceeded to a central processing unit 13 which initiates an interrupt procedure to determine whether there exist any problems in this source power level test. By this procedure, it is conceived that excess electric current is applied to the device 10 and thus the power level test for the device 10 is deemed to be defective.
In practice, in order to increase the amount of electric power that can be provided to a device under test, the electric power source in the semiconductor test system is formed with a plurality of device power sources-connected in a parallel fashion. FIG. 5 shows an example of power source having a plurality of device power sources DPSs to be used for a semiconductor test system. In this example, three DPSs 11A, 11B and 11C are connected in parallel to supply a sum of electric currents the three DPSs to the device 10 that is to be tested.
When an excess electric current of DUT 10 is set to I.sub.Lmax, corresponding excess electric currents I.sub.Amax, I.sub.Bmax and I.sub.Cmax are respectively set in the DPSs 11A, 11B and 11C so as to satisfy I.sub.Lmax =I.sub.Amax +I.sub.Bmax +I.sub.Cmax. As shown in FIG. 5, when the amount of the current to the DUT has not reached the excess electric current, the electric current I.sub.L to be provided to DUT should be I.sub.L =I.sub.A +I.sub.B +I.sub.C, each current of which is proportional to the corresponding maximum (excess) current noted above.
However, in an actual system having parallel power sources, the ratio of current flowing to the DUT from one power source and other power source will vary depending on various factors including differences in internal impedances and output voltages between power sources. Thus, there can be a DPS that drains the excess current and generates an excess current detection signal even though the overall current to the device under test has not reached its excess current. In such a situation, one DPS flows the excess current while the other DPS flows a current lower than its excess current, which results in an inconsistent judgement on the device testing. There even can be a DPS which flows an electric current in a direction opposite to the currents of the other DPSs.
FIG. 6 shows a timing chart depicting the situation associated with the DPS in which an excess electrical current is applied to the device under test. First, when the electric current from the DPS 11A becomes an excess current situation at time t0, the DPS 11A generates an interrupt signal (excess current detection signal) toward a central processor (CPU) 13. In receiving the interrupt signal, the CPU 13 generates an interrupt mask signal (FIG. 6E) during which the other jobs are postponed and reads the conditions of the DPS 11A as well as other DPSs 11B and 11C which are connected in a parallel manner, through an interface (I/O) bus of FIG. 5.
In the case of FIG. 6, the DPSs 11A and 11C are conceived as operating at the predetermined excess currents while the DPS 11B is conceived as operating below the predetermined excess current (11A=NG, 11B=OK, 11C=NG in FIG. 6F). Therefore, the CPU 13 will determine that it is not under the excess current situation as a whole (FIG. 6G), since not all of the DPSs are in the excess current situation. As shown in FIG. 6F, CPU 13 requires the processing time to sequentially determine the situation of the DPSs 11A-11C.
When the above described interrupt job is completed, the CPU 13 resets the interrupt mask signal at time t2 as shown in FIG. 6E. When the intercept mask signal is reset, over current signals (intercept signals) are still generated by DPS 11B and DPS 11C immediately after the time t2. The CPU 13 immediately starts an intercept process and reads the situations of DPS 11A, DPS 11B and DPS 11C which are connected in parallel through the I/O bus. The CPU 13 will conceive that DPS 11A and DPS 11B are in the predetermined excess current condition. However, the CPU 13 will conceive that DPS 11C is under a normal condition flowing the current lower than the predetermined excess current because at the time of reading the situation of DPS 11C, the current of the DPS 11C has returned to normal.
Hence, in the example of FIG. 6, the CPU 13 will determine that the device power source as a whole is not in the situation of excess electric current even though the DUT is under the over current situation during the period between the times t2 and t3. As noted above, in the conventional power source system, there is a possibility of misjudgment in that the system determines that there is no excess electric current even though there is a situation of excess electric current in reality. In FIG. 6, after a time t3, it is shown that the conditions in the DUT electric source is "unknown". This means that excess electric current is not detected for the reason that the device is broken or returned to normal.
As noted above, in the conventional power source system, since the process time is needed for reading the condition of plurality of DPSs through the I/O bus after receiving the interrupt signal from one of the DPSs, there is a problem that the excess electric current may not be detected because of the timing mismatch in the power system. Conversely, even when there is no excess electric current situation, an over current signals may be initiated by one or more of the DPSs and the CPU is interrupted to be used for processing the interrupt job, which lowers the overall ability of the CPU in controlling the overall test procedure.